This invention relates to implementation of shift registers using memory arrays.
Lin et al. U.S. patent application Ser. No. 10/140,312, filed May 6, 2002, shows a technique for using a memory array (e.g., random access memory or “RAM”) to implement a shift register. In this technique special-purpose interconnections are providing in the memory array for selectively routing data read out of one column of the array into another column of the array. This technique also employs a single counter for providing both read and write addresses for the memory array.
The technique shown in the above-mentioned reference has many advantages. There may be some situations, however, in which this technique does not meet a user's needs. For example, the technique in the above-mentioned reference introduces extra switching into the data input path to the memory, which adds to and somewhat complicates the circuitry, and which may also slow down the input path to the memory. Because neither input nor output registers are included in the special-purpose routing that is added to the memory, the memory may have to be operated sub-optimally (i.e., at less than maximum speed) to ensure that no data is lost in routing it from one memory column to the next.